博士（Ph.D.） 计算机系统结构，香港中文大学（CUHK），2010年11月 – 2013年10月

硕士（MPhil） 计算机科学与工程，香港中文大学（CUHK），2008年8月 – 2010年7月

学士（B.S.） 计算机科学与技术，1946伟德国际源自英国（SJTU），2003年9月 – 2007年7月

2021-至今 华为技术有限公司    科学家、高级研究专家（首席） | 异构通信处理器

2020-至今 上海期智研究院        高性能计算杰出科学家

2024-至今 1946伟德国际源自英国           研究员 | 1946伟德国际源自英国

2017-2024 1946伟德国际源自英国          副教授 | 计算机科学与工程系

2014-2017 1946伟德国际源自英国          讲师 | 计算机科学与工程系

2012-2013 美国杜克大学          访问学者

已接收

1. Jiahao Sun, Yijian Zhang, Fangxin Liu, Li Jiang, and Rui Yang, “A Sub-10 μs In-Memory-Search Collision Detection Accelerator Based on RRAM-TCAMs,” to appear in IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025

2. Fangxin Liu, Haomin Li, Bowen Zhu, Zongwu Wang, Zhuoran Song, Haibing Guan, and Li Jiang*. “ASDR: Exploiting Adaptive Sampling and Data Reuse for CIM-based Instant Neural Rendering,” to appear in international conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS, ACM 2026

3. Yilong Zhao, Mingyu Gao, Huanchen Zhang, Fangxin Liu, Gongye Chen, He Xian, Haibing Guan, and Li Jiang*. “PUSHtap: PIM-based In-Memory HTAP with Unified Data Storage Format,” to appear in international conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS, ACM 2026

4. Haomin Li, Fangxin Liu, Zongwu Wang, Ning Yang, Shiyuan Huang, Xiaoyao Liang, and Li Jiang*. “Attack and Defense: Enhancing Robustness of Binary Hyper-Dimensional Computing, “ to appear in ACM Transactions on Architecture and Code Optimization (TACO) , ACM, 2025

5. Haomin Li, Fangxin Liu, Yichi Chen, Zongwu Wang, Shiyuan Huang, Ning Yang, Dongxu Lyu, and Li Jiang*. "FATE: Boosting the Performance of Hyper-Dimensional Computing Intelligence with Flexible Numerical DAta TypE," accepted by ACM International Symposium on Computer Architecture (ISCA), 2025 

6. Fangxin Liu, Haomin Li, Zongwu Wang, Bo Zhang, Mingzhe Zhang, Shoumeng Yan, Li Jiang*, and Haibing Guan, “ALLMod: Exploring Area-Efficiency of LUT-based Large Number Modular Reduction via Hybrid Workloads,” to appear in Design Automation Conference, （DAC）, ACM/IEEE , 2025

7. Zongwu Wang, Peng Xu, Fangxin Liu, Yiwei Hu, Qingxiao Sun, Gezi Li, Cheng Li, Xuan Wang, Li Jiang*, and Haibing Guan, “MILLION: MasterIng Long-Context LLM InferenceVia Outlier-Immunized KV Product OuaNtization,” to appear in Design Automation Conference, （DAC）, ACM/IEEE , 2025

8. Fangxin Liu, Ning Yang, Zongwu Wang, Xuanpeng Zhu, Haidong Yao, Xiankui Xiong, Li Jiang* and Haibing Guan, “BLOOM: Bit-Slice Framework for DNN Acceleration with Mixed-Precision,“ to appear in Design Automation Conference, （DAC）, ACM/IEEE , 2025

已发表

2025

[1]. He, Houshu, Gang Li, Fangxin Liu, Li Jiang, Xiaoyao Liang, and Zhuoran Song. 2025. “GSArch: Breaking Memory Barriers in 3D Gaussian Splatting Training via Architectural Support.” Pp. 366–79 in IEEE International Symposium on High Performance Computer Architecture, HPCA 2025, Las Vegas, NV, USA, March 1-5, 2025. IEEE.

[2]. Huang, Shiyuan, Fangxin Liu, Tian Li, Zongwu Wang, Ning Yang, Haomin Li, and Li Jiang*. 2025. “STCO: Enhancing Training Efficiency via Structured Sparse Tensor Compilation Optimization.” ACM Trans. Design Autom. Electr. Syst. 30(1):1–22. doi: 10.1145/3701033.

[3]. Huang, Shiyuan, Fangxin Liu, Tao Yang, Zongwu Wang, Ning Yang, and Li Jiang*. 2025. “SpMMPlu-Pro: An Enhanced Compiler Plug-In for Efficient SpMM and Sparsity Propagation Algorithm.” IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 44(2):669–83. doi: 10.1109/TCAD.2024.3446718.

[4]. Li, Haomin, Fangxin Liu, Zewen Sun, Zongwu Wang, Shiyuan Huang, Ning Yang, and Li Jiang*. 2025. “NeuronQuant: Accurate and Efficient Post-Training Quantization for Spiking Neural Networks.” Pp. 734–40 in Proceedings of the 30th Asia and South Pacific Design Automation Conference, ASPDAC 2025, Tokyo, Japan, January 20-23, 2025, edited by Y. Nakamura and Y. Wang. ACM.

[5]. Liu, Fangxin, Shiyuan Huang, Ning Yang, Zongwu Wang, Haomin Li, and Li Jiang*. 2025. “CROSS: Compiler-Driven Optimization of Sparse DNNs Using Sparse/Dense Computation Kernels.” Pp. 963–76 in IEEE International Symposium on High Performance Computer Architecture, HPCA 2025, Las Vegas, NV, USA, March 1-5, 2025. IEEE.

[6]. Liu, Fangxin, Zongwu Wang, Peng Xu, Shiyuan Huang, and Li Jiang*. 2025. “Exploiting Differential-Based Data Encoding for Enhanced Query Efficiency.” Pp. 594–600 in Proceedings of the 30th Asia and South Pacific Design Automation Conference, ASPDAC 2025, Tokyo, Japan, January 20-23, 2025, edited by Y. Nakamura and Y. Wang. ACM.

2024

[7]. Huang, Shiyuan, Fangxin Liu, Tian Li, Zongwu Wang, Haomin Li, and Li Jiang*. 2024. “TSTC: Enabling Efficient Training via Structured Sparse Tensor Compilation.” Pp. 884–89 in Proceedings of the 29th Asia and South Pacific Design Automation Conference, ASPDAC 2024, Incheon, Korea, January 22-25, 2024. IEEE.

[8]. Li, Haomin, Fangxin Liu, Yichi Chen, and Li Jiang*. 2024. “HyperFeel: An Efficient Federated Learning Framework Using Hyperdimensional Computing.” Pp. 716–21 in Proceedings of the 29th Asia and South Pacific Design Automation Conference, ASPDAC 2024, Incheon, Korea, January 22-25, 2024. IEEE.

[9]. Liu, Fangxin, Shiyuan Huang, Longyu Zhao, Li Jiang, and Zongwu Wang. 2024. “LowPASS: A Low Power PIM-Based Accelerator with Speculative Scheme for SNNs.” Pp. 1–6 in Proceedings of the 29th ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED 2024, Newport Beach, CA, USA, August 5-7, 2024, edited by P. Meinerzhagen, K. Dev, and J. Yoo. ACM.

[10]. Liu, Fangxin, Haomin Li, Ning Yang, Yichi Chen, Zongwu Wang, Tao Yang, and Li Jiang*. 2024. “PAAP-HD: PIM-Assisted Approximation for Efficient Hyper-Dimensional Computing.” Pp. 46–51 in Proceedings of the 29th Asia and South Pacific Design Automation Conference, ASPDAC 2024, Incheon, Korea, January 22-25, 2024. IEEE.

[11]. Liu, Fangxin, Haomin Li, Ning Yang, Zongwu Wang, Tao Yang, and Li Jiang*. 2024. “TEAS: Exploiting Spiking Activity for Temporal-Wise Adaptive Spiking Neural Networks.” Pp. 842–47 in Proceedings of the 29th Asia and South Pacific Design Automation Conference, ASPDAC 2024, Incheon, Korea, January 22-25, 2024. IEEE.

[12]. Liu, Fangxin, Zongwu Wang, Wenbo Zhao, Ning Yang, Yongbiao Chen, Shiyuan Huang, Haomin Li, Tao Yang, Songwen Pei, Xiaoyao Liang and Li Jiang*. 2024. “Exploiting Temporal-Unrolled Parallelism for Energy-Efficient SNN Acceleration.” IEEE Transactions on Parallel and Distributed Systems 35(10):16.

[13]. Liu, Fangxin, Ning Yang, Haomin Li, Zongwu Wang, Zhuoran Song, Songwen Pei, and Li Jiang*. 2024. “SPARK: Scalable and Precision-Aware Acceleration of Neural Networks via Efficient Encoding.” Pp. 1029–42 in IEEE International Symposium on High-Performance Computer Architecture, HPCA 2024, Edinburgh, United Kingdom, March 2-6, 2024. IEEE.

[14]. Liu, Fangxin, Ning Yang, Zhiyan Song, Zongwu Wang, and Li Jiang*. 2024. “HOLES: Boosting Large Language Models Efficiency with Hardware-Friendly Lossless Encoding.” Pp. 207–14 in 42nd IEEE International Conference on Computer Design, ICCD 2024, Milan, Italy, November 18-20, 2024. IEEE.

[15]. Liu, Fangxin, Ning Yang, Zhiyan Song, Zongwu Wang, Haomin Li, Shiyuan Huang, Zhuoran Song, Songwen Pei, and Li Jiang*. 2024. “INSPIRE: Accelerating Deep Neural Networks via Hardware-Friendly Index-Pair Encoding.” P. 10:1-10:6 in Proceedings of the 61st ACM/IEEE Design Automation Conference, DAC 2024, San Francisco, CA, USA, June 23-27, 2024, edited by V. De. ACM.

[16]. Liu, Fangxin, Wenbo Zhao, Zongwu Wang, Yongbiao Chen, Xiaoyao Liang, and Li Jiang*. 2024. “ERA-BS: Boosting the Efficiency of ReRAM-Based PIM Accelerator With Fine-Grained Bit-Level Sparsity.” IEEE Trans. Computers 73(9):2320–34. doi: 10.1109/TC.2023.3290869.

[17]. Nie, Chen, Chenyu Tang, Jie Lin, Huan Hu, Chenyang Lv, Ting Cao, Weifeng Zhang, Li Jiang, Xiaoyao Liang, Weikang Qian, Yanan Sun, and Zhezhi He. 2024. “VSPIM: SRAM Processing-in-Memory DNN Acceleration via Vector-Scalar Operations.” IEEE Trans. Computers 73(10):2378–90. doi: 10.1109/TC.2023.3285095.

[18]. Song, Zhuoran, Houshu He, Fangxin Liu, Yifan Hao, Xinkai Song, Li Jiang, and Xiaoyao Liang. 2024. “SRender: Boosting Neural Radiance Field Efficiency via Sensitivity-Aware Dynamic Precision Rendering.” Pp. 525–37 in 57th IEEE/ACM International Symposium on Microarchitecture, MICRO 2024, Austin, TX, USA, November 2-6, 2024. IEEE.

[19]. Song, Zhuoran, Zhongkai Yu, Xinkai Song, Yifan Hao, Li Jiang, Naifeng Jing, and Xiaoyao Liang. 2024. “Environmental Condition Aware Super-Resolution Acceleration Framework in Server-Client Hierarchies.” ACM Trans. Archit. Code Optim. 21(4):65:1-65:26. doi: 10.1145/3678008.

[20]. Sun, Jiahao, Fangxin Liu, Yijian Zhang, Li Jiang, and Rui Yang. 2024. “RTSA: An RRAM-TCAM Based In-Memory-Search Accelerator for Sub-100 \(\mathrm\mu\)s Collision Detection.” Pp. 1–2 in Design, Automation & Test in Europe Conference & Exhibition, DATE 2024, Valencia, Spain, March 25-27, 2024. IEEE.

[21]. Tian, Boyu, Yiwei Li, Li Jiang, Shuangyu Cai, and Mingyu Gao. 2024. “NDPBridge: Enabling Cross-Bank Coordination in Near-DRAM-Bank Processing Architectures.” Pp. 628–43 in 51st ACM/IEEE Annual International Symposium on Computer Architecture, ISCA 2024, Buenos Aires, Argentina, June 29 - July 3, 2024. IEEE.

[22]. Wang, Zongwu, Fangxin Liu, Xin Tang, and Li Jiang*. 2024. “PS4: A Low Power SNN Accelerator with Spike Speculative Scheme.” Pp. 76–83 in 42nd IEEE International Conference on Computer Design, ICCD 2024, Milan, Italy, November 18-20, 2024. IEEE.

[23]. Wang, Zongwu, Fangxin Liu, Ning Yang, Shiyuan Huang, Haomin Li, and Li Jiang*. 2024. “COMPASS: SRAM-Based Computing-in-Memory SNN Accelerator with Adaptive Spike Speculation.” Pp. 1090–1106 in 57th IEEE/ACM International Symposium on Microarchitecture, MICRO 2024, Austin, TX, USA, November 2-6, 2024. IEEE.

[24]. Yang, Ning, Fangxin Liu, Zongwu Wang, Haomin Li, Zhuoran Song, Songwen Pei, and Li Jiang*. 2024. “EOS: An Energy-Oriented Attack Framework for Spiking Neural Networks.” P. 58:1-58:6 in Proceedings of the 61st ACM/IEEE Design Automation Conference, DAC 2024, San Francisco, CA, USA, June 23-27, 2024, edited by V. De. ACM.

[25]. Yang, Ning, Fangxin Liu, Zongwu Wang, Zhiyan Song, Tao Yang, and Li Jiang*. 2024. “T-BUS: Taming Bipartite Unstructured Sparsity for Energy-Efficient DNN Acceleration.” Pp. 68–75 in 42nd IEEE International Conference on Computer Design, ICCD 2024, Milan, Italy, November 18-20, 2024. IEEE.

[26]. Yang, Ning, Fangxin Liu, Zongwu Wang, Junping Zhao, and Li Jiang*. 2024. “SearchQ: Search-Based Fine-Grained Quantization for Data-Free Model Compression.” IEEE Transactions on Circuits and Systems for Artificial Intelligence 1(2):220–28. doi: 10.1109/TCASAI.2024.3491941.

[27]. Zhang, Xuan, Zhuoran Song, Xing Li, Zhezhi He, Naifeng Jing, Li Jiang, and Xiaoyao Liang. 2024. “Watt: A Write-Optimized RRAM-Based Accelerator for Attention.” Pp. 107–20 in Euro-Par 2024: Parallel Processing - 30th European Conference on Parallel and Distributed Processing, Madrid, Spain, August 26-30, 2024, Proceedings, Part II. Vol. 14802, Lecture Notes in Computer Science, edited by J. Carretero, S. Shende, J. García-Blas, I. Brandic, K. Olcoz, and M. Schreiber. Springer.

[28]. Zhang, Xuan, Zhuoran Song, Peng Zhou, Xing Li, Xueyuan Liu, Xiaolong Lin, Zhezhi He, Li Jiang, Naifeng Jing, and Xiaoyao Liang. 2024. “Early: An Importance-Aware Early Firing and Exit for SNN Acceleration.” Pp. 624–27 in 42nd IEEE International Conference on Computer Design, ICCD 2024, Milan, Italy, November 18-20, 2024. IEEE.

[29]. Zhao, Longyu, Zongwu Wang, Fangxin Liu, and Li Jiang*. 2024. “Ninja: A Hardware Assisted System for Accelerating Nested Address Translation.” Pp. 426–33 in 42nd IEEE International Conference on Computer Design, ICCD 2024, Milan, Italy, November 18-20, 2024. IEEE.

[30]. Zhao, Yilong, Mingyu Gao, Fangxin Liu, Yiwei Hu, Zongwu Wang, Han Lin, Jin Li, He Xian, Hanlin Dong, Tao Yang, Naifeng Jing, Xiaoyao Liang, and Li Jiang*. 2024. “UM-PIM: DRAM-Based PIM with Uniform & Shared Memory Space.” Pp. 644–59 in 51st ACM/IEEE Annual International Symposium on Computer Architecture, ISCA 2024, Buenos Aires, Argentina, June 29 - July 3, 2024. IEEE.

2023

[31]. Li, Haomin, Fangxin Liu, Yichi Chen, and Li Jiang*. 2023. “HyperNode: An Efficient Node Classification Framework Using HyperDimensional Computing.” Pp. 1–9 in IEEE/ACM International Conference on Computer Aided Design, ICCAD 2023, San Francisco, CA, USA, October 28 - Nov. 2, 2023. IEEE.

[32]. Liu, Fangxin, Haomin Li, Yongbiao Chen, Tao Yang, and Li Jiang*. 2023. “HyperAttack: An Efficient Attack Framework for HyperDimensional Computing.” Pp. 1–6 in 60th ACM/IEEE Design Automation Conference, DAC 2023, San Francisco, CA, USA, July 9-13, 2023. IEEE.

[33]. Liu, Fangxin, Zongwu Wang, Yongbiao Chen, Zhezhi He, Tao Yang, Xiaoyao Liang, and Li Jiang*. 2023. “SoBS-X: Squeeze-Out Bit Sparsity for ReRAM-Crossbar-Based Neural Network Accelerator.” IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(1):204–17. doi: 10.1109/TCAD.2022.3172907.

[34]. Liu, Fangxin, Ning Yang, and Li Jiang*. 2023. “PSQ: An Automatic Search Framework for Data-Free Quantization on PIM-Based Architecture.” Pp. 507–14 in 41st IEEE International Conference on Computer Design, ICCD 2023, Washington, DC, USA, November 6-8, 2023. IEEE.

[35]. Liu, Fangxin, Wenbo Zhao, Zongwu Wang, Xiaokang Yang, and Li Jiang*. 2023. “SIMSnn: A Weight-Agnostic ReRAM-Based Search-In-Memory Engine for SNN Acceleration.” Pp. 1–2 in Design, Automation & Test in Europe Conference & Exhibition, DATE 2023, Antwerp, Belgium, April 17-19, 2023. IEEE.

[36]. Song, Zhuoran, Heng Lu, Li Jiang, Naifeng Jing, and Xiaoyao Liang. 2023. “Real-Time Video Recognition via Decoder-Assisted Neural Network Acceleration Framework.” IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(7):2238–51. doi: 10.1109/TCAD.2022.3217667.

[37]. Song, Zhuoran, Heng Lu, Gang Li, Li Jiang, Naifeng Jing, and Xiaoyao Liang. 2023. “PRADA: Point Cloud Recognition Acceleration via Dynamic Approximation.” Pp. 1–6 in Design, Automation & Test in Europe Conference & Exhibition, DATE 2023, Antwerp, Belgium, April 17-19, 2023. IEEE.

[38]. Yang, Tao, Dongyue Li, Fei Ma, Zhuoran Song, Yilong Zhao, Jiaxi Zhang, Fangxin Liu, and Li Jiang*. 2023. “PASGCN: An ReRAM-Based PIM Design for GCN With Adaptively Sparsified Graphs.” IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(1):150–63. doi: 10.1109/TCAD.2022.3175031.

[39]. Yang, Tao, Fei Ma, Xiaoling Li, Fangxin Liu, Yilong Zhao, Zhezhi He, and Li Jiang*. 2023. “DTATrans: Leveraging Dynamic Token-Based Quantization With Accuracy Compensation Mechanism for Efficient Transformer Architecture.” IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(2):509–20. doi: 10.1109/TCAD.2022.3181541.

[40]. Yang, Tao, Hui Ma, Yilong Zhao, Fangxin Liu, Zhezhi He, Xiaoli Sun, and Li Jiang*. 2023. “PIMPR: PIM-Based Personalized Recommendation with Heterogeneous Memory Hierarchy.” Pp. 1–6 in Design, Automation & Test in Europe Conference & Exhibition, DATE 2023, Antwerp, Belgium, April 17-19, 2023. IEEE.

[41]. Yang, Tao, Yiyuan Zhou, Qidong Tang, Feng Xu, Hui Ma, Jieru Zhao, and Li Jiang*. 2023. “SpMMPlu: A Compiler Plug-in with Sparse IR for Efficient Sparse Matrix Multiplication.” Pp. 1–6 in 60th ACM/IEEE Design Automation Conference, DAC 2023, San Francisco, CA, USA, July 9-13, 2023. IEEE.

[42]. Ye, Yaoyao, Zixuan Liu, Jungan Liu, and Li Jiang*. 2023. “ASDR: An Application-Specific Deadlock-Free Routing for Chiplet-Based Systems.” Pp. 46–51 in Proceedings of the 16th International Workshop on Network on Chip Architectures, NoCArc 2023, Toronto, ON, Canada, 28 October 2023. ACM.

[43]. Zhang, Xuan, Zhuoran Song, Xing Li, Zhezhi He, Li Jiang, Naifeng Jing, and Xiaoyao Liang. 2023. “HyAcc: A Hybrid CAM-MAC RRAM-Based Accelerator for Recommendation Model.” Pp. 375–82 in 41st IEEE International Conference on Computer Design, ICCD 2023, Washington, DC, USA, November 6-8, 2023. IEEE.

2022

[44]. Cao, Weidong, Yilong Zhao, Adith Boloor, Yinhe Han, Xuan Zhang, and Li Jiang*. 2022. “Neural-PIM: Efficient Processing-In-Memory With Neural Approximation of Peripherals.” IEEE Trans. Computers 71(9):2142–55. doi: 10.1109/TC.2021.3122905.

[45]. Gong, Yu, Zhihan Xu, Zhezhi He, Weifeng Zhang, Xiaobing Tu, Xiaoyao Liang, and Li Jiang*. 2022. “N3H-Core: Neuron-Designed Neural Network Accelerator via FPGA-Based Heterogeneous Computing Cores.” Pp. 112–22 in FPGA ’22: The 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Virtual Event, USA, 27 February 2022 - 1 March 2022, edited by M. Adler and P. Ienne. ACM.

[46]. Liu, Fangxin, Haomin Li, Xiaokang Yang, and Li Jiang*. 2022. “L3E-HD: A Framework Enabling Efficient Ensemble in High-Dimensional Space for Language Tasks.” Pp. 1844–48 in SIGIR ’22: The 45th International ACM SIGIR Conference on Research and Development in Information Retrieval, Madrid, Spain, July 11 - 15, 2022, edited by E. Amigó, P. Castells, J. Gonzalo, B. Carterette, J. S. Culpepper, and G. Kazai. ACM.

[47]. Liu, Fangxin, Zongwu Wang, Wenbo Zhao, Yongbiao Chen, Tao Yang, Xiaokang Yang, and Li Jiang*. 2022. “Randomize and Match: Exploiting Irregular Sparsity for Energy Efficient Processing in SNNs.” Pp. 451–54 in IEEE 40th International Conference on Computer Design, ICCD 2022, Olympic Valley, CA, USA, October 23-26, 2022. IEEE.

[48]. Liu, Fangxin, Wenbo Zhao, Yongbiao Chen, Zongwu Wang, Zhezhi He, Rui Yang, Qidong Tang, Tao Yang, Cheng Zhuo, and Li Jiang*. 2022. “PIM-DH: ReRAM-Based Processing-in-Memory Architecture for Deep Hashing Acceleration.” Pp. 1087–92 in DAC ’22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10 - 14, 2022, edited by R. Oshana. ACM.

[49]. Liu, Fangxin, Wenbo Zhao, Yongbiao Chen, Zongwu Wang, and Li Jiang*. 2022. “SpikeConverter: An Efficient Conversion Framework Zipping the Gap between Artificial Neural Networks and Spiking Neural Networks.” Pp. 1692–1701 in Thirty-Sixth AAAI Conference on Artificial Intelligence, AAAI 2022, Thirty-Fourth Conference on Innovative Applications of Artificial Intelligence, IAAI 2022, The Twelveth Symposium on Educational Advances in Artificial Intelligence, EAAI 2022 Virtual Event, February 22 - March 1, 2022. AAAI Press.

[50]. Liu, Fangxin, Wenbo Zhao, Zongwu Wang, Yongbiao Chen, Zhezhi He, Naifeng Jing, Xiaoyao Liang, and Li Jiang*. 2022. “EBSP: Evolving Bit Sparsity Patterns for Hardware-Friendly Inference of Quantized Deep Neural Networks.” Pp. 259–64 in DAC ’22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10 - 14, 2022, edited by R. Oshana. ACM.

[51]. Liu, Fangxin, Wenbo Zhao, Zongwu Wang, Yongbiao Chen, Tao Yang, Zhezhi He, Xiaokang Yang, and Li Jiang*. 2022. “SATO: Spiking Neural Network Acceleration via Temporal-Oriented Dataflow and Architecture.” Pp. 1105–10 in DAC ’22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10 - 14, 2022, edited by R. Oshana. ACM.

[52]. Liu, Fangxin, Wenbo Zhao, Zongwu Wang, Yilong Zhao, Tao Yang, Yiran Chen, and Li Jiang*. 2022. “IVQ: In-Memory Acceleration of DNN Inference Exploiting Varied Quantization.” IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(12):5313–26. doi: 10.1109/TCAD.2022.3156017.

[53]. Nie, Chen, Zongwu Wang, Qidong Tang, Chenyang Lv, Li Jiang, and Zhezhi He. 2022. “Cross-Layer Designs against Non-Ideal Effects in ReRAM-Based Processing-in-Memory System.” Pp. 1–6 in 23rd International Symposium on Quality Electronic Design, ISQED 2022, Santa Clara, CA, USA, April 6-7, 2022. IEEE.

[54]. Tang, Qidong, Zhezhi He, Fangxin Liu, Zongwu Wang, Yiyuan Zhou, Yinghuan Zhang, and Li Jiang*. 2022. “HAWIS: Hardware-Aware Automated WIdth Search for Accurate, Energy-Efficient and Robust Binary Neural Network on ReRAM Dot-Product Engine.” Pp. 226–31 in 27th Asia and South Pacific Design Automation Conference, ASP-DAC 2022, Taipei, Taiwan, January 17-20, 2022. IEEE.

[55]. Wang, Zongwu, Zhezhi He, Rui Yang, Shiquan Fan, Jie Lin, Fangxin Liu, Yueyang Jia, Chenxi Yuan, Qidong Tang, and Li Jiang*. 2022. “Self-Terminating Write of Multi-Level Cell ReRAM for Efficient Neuromorphic Computing.” Pp. 1251–56 in 2022 Design, Automation & Test in Europe Conference & Exhibition, DATE 2022, Antwerp, Belgium, March 14-23, 2022, edited by C. Bolchini, I. Verbauwhede, and E.-I. Vatajelu. IEEE.

[56]. Yang, Tao, Dongyue Li, Zhuoran Song, Yilong Zhao, Fangxin Liu, Zongwu Wang, Zhezhi He, and Li Jiang*. 2022. “DTQAtten: Leveraging Dynamic Token-Based Quantization for Efficient Attention Architecture.” Pp. 700–705 in 2022 Design, Automation & Test in Europe Conference & Exhibition, DATE 2022, Antwerp, Belgium, March 14-23, 2022, edited by C. Bolchini, I. Verbauwhede, and E.-I. Vatajelu. IEEE.

2021

[57]. Guo, Hanchen, Zhehan Lin, Yunfei Gu, Chentao Wu, Li Jiang, Jie Li, Guangtao Xue, and Minyi Guo. 2021. “Lazy-WL: A Wear-Aware Load Balanced Data Redistribution Method for Efficient SSD Array Scaling.” Pp. 157–68 in IEEE International Conference on Cluster Computing, CLUSTER 2021, Portland, OR, USA, September 7-10, 2021. IEEE.

[58]. Hong, Yunyan, Ailing Zeng, Min Li, Cewu Lu, Li Jiang, and Qiang Xu. 2021. “Skimming and Scanning for Efficient Action Recognition in Untrimmed Videos.” Pp. 1–10 in 14th International Congress on Image and Signal Processing, BioMedical Engineering and Informatics, CISP-BMEI 2021, Shanghai, China, October 23-25, 2021. IEEE.

[59]. Li, Dongyue, Tao Yang, Lun Du, Zhezhi He, and Li Jiang*. 2021. “AdaptiveGCN: Efficient GCN Through Adaptively Sparsifying Graphs.” Pp. 3206–10 in CIKM ’21: The 30th ACM International Conference on Information and Knowledge Management, Virtual Event, Queensland, Australia, November 1 - 5, 2021, edited by G. Demartini, G. Zuccon, J. S. Culpepper, Z. Huang, and H. Tong. ACM.

[60]. Li, Min, Yu Li, Ye Tian, Li Jiang, and Qiang Xu. 2021. “AppealNet: An Efficient and Highly-Accurate Edge/Cloud Collaborative Architecture for DNN Inference.” Pp. 409–14 in 58th ACM/IEEE Design Automation Conference, DAC 2021, San Francisco, CA, USA, December 5-9, 2021. IEEE.

[61]. Liu, Fangxin, Wenbo Zhao, Zhezhi He, Yanzhi Wang, Zongwu Wang, Changzhi Dai, Xiaoyao Liang, and Li Jiang*. 2021. “Improving Neural Network Efficiency via Post-Training Quantization with Adaptive Floating-Point.” Pp. 5261–70 in 2021 IEEE/CVF International Conference on Computer Vision, ICCV 2021, Montreal, QC, Canada, October 10-17, 2021. IEEE.

[62]. Liu, Fangxin, Wenbo Zhao, Zhezhi He, Zongwu Wang, Yilong Zhao, Yongbiao Chen, and Li Jiang*. 2021. “Bit-Transformer: Transforming Bit-Level Sparsity into Higher Preformance in ReRAM-Based Accelerator.” Pp. 1–9 in IEEE/ACM International Conference On Computer Aided Design, ICCAD 2021, Munich, Germany, November 1-4, 2021. IEEE.

[63]. Liu, Fangxin, Wenbo Zhao, Zhezhi He, Zongwu Wang, Yilong Zhao, Tao Yang, Jingnai Feng, Xiaoyao Liang, and Li Jiang*. 2021. “SME: ReRAM-Based Sparse-Multiplication-Engine to Squeeze-Out Bit Sparsity of Neural Network.” Pp. 417–24 in 39th IEEE International Conference on Computer Design, ICCD 2021, Storrs, CT, USA, October 24-27, 2021. IEEE.

[64]. Liu, Fangxin, Wenbo Zhao, Zongwu Wang, Tao Yang, and Li Jiang*. 2021. “IM3A: Boosting Deep Neural Network Efficiency via In-Memory Addressing-Assisted Acceleration.” Pp. 253–58 in GLSVLSI ’21: Great Lakes Symposium on VLSI 2021, Virtual Event, USA, June 22-25, 2021, edited by Y. Chen, V. V. Zhirnov, A. Sasan, and I. Savidis. ACM.

[65]. Meng, Ziqi, Weikang Qian, Yilong Zhao, Yanan Sun, Rui Yang, and Li Jiang*. 2021. “Digital Offset for RRAM-Based Neuromorphic Computing: A Novel Solution to Conquer Cycle-to-Cycle Variation.” Pp. 1078–83 in Design, Automation & Test in Europe Conference & Exhibition, DATE 2021, Grenoble, France, February 1-5, 2021. IEEE.

[66]. Nie, Chen, Jie Lin, Huan Hu, Li Jiang, Xiaoyao Liang, and Zhezhi He. 2021. “Energy-Efficient Hybrid-RAM with Hybrid Bit-Serial Based VMM Support.” Pp. 347–52 in GLSVLSI ’21: Great Lakes Symposium on VLSI 2021, Virtual Event, USA, June 22-25, 2021, edited by Y. Chen, V. V. Zhirnov, A. Sasan, and I. Savidis. ACM.

[67]. Shen, Tianhong, Yanan Sun, Weifeng He, Zhi Li, Weiyi Liu, Zhezhi He, and Li Jiang*. 2021. “A Ternary Memristive Logic-in-Memory Design for Fast Data Scan.” Pp. 183–84 in 2021 IEEE International Conference on Integrated Circuits, Technologies and Applications, ICTA 2021, Zhuhai, China, November 24-26, 2021. IEEE.

[68]. Song, Zhuoran, Dongyue Li, Zhezhi He, Xiaoyao Liang, and Li Jiang*. 2021. “ReRAM-Sharing: Fine-Grained Weight Sharing for ReRAM-Based Deep Neural Network Accelerator.” Pp. 1–5 in IEEE International Symposium on Circuits and Systems, ISCAS 2021, Daegu, South Korea, May 22-28, 2021. IEEE.

[69]. Song, Zhuoran, Yanan Sun, Lerong Chen, Tianjian Li, Naifeng Jing, Xiaoyao Liang, and Li Jiang*. 2021. “ITT-RNA: Imperfection Tolerable Training for RRAM-Crossbar-Based Deep Neural-Network Accelerator.” IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(1):129–42. doi: 10.1109/TCAD.2020.2989373.

[70]. Sun, Yanan, Chang Ma, Zhi Li, Yilong Zhao, Jiachen Jiang, Weikang Qian, Rui Yang, Zhezhi He, and Li Jiang*. 2021. “Unary Coding and Variation-Aware Optimal Mapping Scheme for Reliable ReRAM-Based Neuromorphic Computing.” IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(12):2495–2507. doi: 10.1109/TCAD.2021.3051856.

[71]. Wang, Xingyi, Yu Li, Yiquan Chen, Shiwen Wang, Yin Du, Cheng He, Yuzhong Zhang, Pinan Chen, Xin Li, Wenjun Song, Qiang Xu, and Li Jiang*. 2021. “On Workload-Aware DRAM Failure Prediction in Large-Scale Data Centers.” Pp. 1–6 in 39th IEEE VLSI Test Symposium, VTS 2021, San Diego, CA, USA, April 25-28, 2021. IEEE.

[72]. Wu, Feiyang, Zhuoran Song, Jing Ke, Li Jiang, Naifeng Jing, and Xiaoyao Liang. 2021. “PIPArch: Programmable Image Processing Architecture Using Sliding Array.” Pp. 73–80 in 2021 IEEE Intl Conf on Parallel & Distributed Processing with Applications, Big Data & Cloud Computing, Sustainable Computing & Communications, Social Computing & Networking (ISPA/BDCloud/SocialCom/SustainCom), New York City, NY, USA, September 30 - Oct. 3, 2021. IEEE.

[73]. Yang, Tao, Zhezhi He, Tengchuan Kou, Qingzheng Li, Qi Han, Haibao Yu, Fangxin Liu, Yun Liang, and Li Jiang*. 2021. “BISWSRBS: A Winograd-Based CNN Accelerator with a Fine-Grained Regular Sparsity Pattern and Mixed Precision Quantization.” ACM Trans. Reconfigurable Technol. Syst. 14(4):18:1-18:28. doi: 10.1145/3467476.

[74]. Yang, Tao, Dongyue Li, Yibo Han, Yilong Zhao, Fangxin Liu, Xiaoyao Liang, Zhezhi He, and Li Jiang*. 2021. “PIMGCN: A ReRAM-Based PIM Design for Graph Convolutional Network Acceleration.” Pp. 583–88 in 58th ACM/IEEE Design Automation Conference, DAC 2021, San Francisco, CA, USA, December 5-9, 2021. IEEE.

[75]. Zhao, Yilong, Zhezhi He, Naifeng Jing, Xiaoyao Liang, and Li Jiang*. 2021. “Re2PIM: A Reconfigurable ReRAM-Based PIM Design for Variable-Sized Vector-Matrix Multiplication.” Pp. 15–20 in GLSVLSI ’21: Great Lakes Symposium on VLSI 2021, Virtual Event, USA, June 22-25, 2021, edited by Y. Chen, V. V. Zhirnov, A. Sasan, and I. Savidis. ACM.

[76]. Zhong, Hongtao, Shengjie Cao, Li Jiang, Xia An, Vijaykrishnan Narayanan, Yongpan Liu, Huazhong Yang, and Xueqing Li. 2021. “DyTAN: Dynamic Ternary Content Addressable Memory Using Nanoelectromechanical Relays.” IEEE Trans. Very Large Scale Integr. Syst. 29(11):1981–93. doi: 10.1109/TVLSI.2021.3115622.

2020

[77]. Chu, Chaoqun, Yanzhi Wang, Yilong Zhao, Xiaolong Ma, Shaokai Ye, Yunyan Hong, Xiaoyao Liang, Yinhe Han, and Li Jiang*. 2020. “PIM-Prune: Fine-Grain DCNN Pruning for Crossbar-Based Process-In-Memory Architecture.” Pp. 1–6 in 57th ACM/IEEE Design Automation Conference, DAC 2020, San Francisco, CA, USA, July 20-24, 2020. IEEE.

[78]. Ma, Chang, Yanan Sun, Weikang Qian, Ziqi Meng, Rui Yang, and Li Jiang*. 2020. “Go Unary: A Novel Synapse Coding and Mapping Scheme for Reliable ReRAM-Based Neuromorphic Computing.” Pp. 1432–37 in 2020 Design, Automation & Test in Europe Conference & Exhibition, DATE 2020, Grenoble, France, March 9-13, 2020. IEEE.

[79]. Song, Zhuoran, Bangqi Fu, Feiyang Wu, Zhaoming Jiang, Li Jiang, Naifeng Jing, and Xiaoyao Liang. 2020. “DRQ: Dynamic Region-Based Quantization for Deep Neural Network Acceleration.” Pp. 1010–21 in 47th ACM/IEEE Annual International Symposium on Computer Architecture, ISCA 2020, Virtual Event / Valencia, Spain, May 30 - June 3, 2020. IEEE.

[80]. Song, Zhuoran, Jianfei Wang, Tianjian Li, Li Jiang, Jing Ke, Xiaoyao Liang, and Naifeng Jing. 2020. “GPNPU: Enabling Efficient Hardware-Based Direct Convolution with Multi-Precision Support in GPU Tensor Cores.” Pp. 1–6 in 57th ACM/IEEE Design Automation Conference, DAC 2020, San Francisco, CA, USA, July 20-24, 2020. IEEE.

[81]. Song, Zhuoran, Yilong Zhao, Yanan Sun, Xiaoyao Liang, and Li Jiang*. 2020. “ESNreram: An Energy-Efficient Sparse Neural Network Based on Resistive Random-Access Memory.” Pp. 291–96 in GLSVLSI ’20: Great Lakes Symposium on VLSI 2020, Virtual Event, China, September 7-9, 2020, edited by T. Mohsenin, W. Zhao, Y. Chen, and O. Mutlu. ACM.

[82]. Wang, Xingyi, Li Jiang*, and Krishnendu Chakrabarty. 2020. “LSTM-Based Analysis of Temporally- and Spatially-Correlated Signatures for Intermittent Fault Detection.” Pp. 1–6 in 38th IEEE VLSI Test Symposium, VTS 2020, San Diego, CA, USA, April 5-8, 2020. IEEE.

[83]. Yan, Qi, Li Jiang*, and Solmaz S. Kia. 2020. “Measurement Scheduling for Cooperative Localization in Resource-Constrained Conditions.” IEEE Robotics Autom. Lett. 5(2):1991–98. doi: 10.1109/LRA.2020.2969916.

[84]. Yang, Tao, Yunkun Liao, Jianping Shi, Yun Liang, Naifeng Jing, and Li Jiang*. 2020. “A Winograd-Based CNN Accelerator with a Fine-Grained Regular Sparsity Pattern.” Pp. 254–61 in 30th International Conference on Field-Programmable Logic and Applications, FPL 2020, Gothenburg, Sweden, August 31 - September 4, 2020, edited by N. Mentens, L. Sousa, P. Trancoso, M. Pericàs, and I. Sourdis. IEEE.

2019

[85]. Ji, Houxiang, Li Jiang*, Tianjian Li, Naifeng Jing, Jing Ke, and Xiaoyao Liang. 2019. “HUBPA: High Utilization Bidirectional Pipeline Architecture for Neuromorphic Computing.” Pp. 249–54 in Proceedings of the 24th Asia and South Pacific Design Automation Conference, ASPDAC 2019, Tokyo, Japan, January 21-24, 2019, edited by T. Shibuya. ACM.

[86]. Jiang, Li, Zhuoran Song, Haiyue Song, Chengwen Xu, Qiang Xu, Naifeng Jing, Weifeng Zhang, and Xiaoyao Liang. 2019. “Energy-Efficient and Quality-Assured Approximate Computing Framework Using a Co-Training Method.” ACM Trans. Design Autom. Electr. Syst. 24(6):59:1-59:25. doi: 10.1145/3342239.

[87]. Song, Zhuoran, Ru Wang, Dongyu Ru, Zhenghao Peng, Hongru Huang, Hai Zhao, Xiaoyao Liang, and Li Jiang*. 2019. “Approximate Random Dropout for DNN Training Acceleration in GPGPU.” Pp. 108–13 in Design, Automation & Test in Europe Conference & Exhibition, DATE 2019, Florence, Italy, March 25-29, 2019, edited by J. Teich and F. Fummi. IEEE.

[88]. Sun, Xiaoyi, Krishnendu Chakrabarty, Ruirui Huang, Yiquan Chen, Bing Zhao, Hai Cao, Yinhe Han, Xiaoyao Liang, and Li Jiang*. 2019. “System-Level Hardware Failure Prediction Using Deep Learning.” P. 20 in Proceedings of the 56th Annual Design Automation Conference 2019, DAC 2019, Las Vegas, NV, USA, June 02-06, 2019. ACM.

[89]. Sun, Yanan, Jiawei Gu, Weifeng He, Qin Wang, Naifeng Jing, Zhigang Mao, Weikang Qian, and Li Jiang*. 2019. “Energy-Efficient Nonvolatile SRAM Design Based on Resistive Switching Multi-Level Cells.” IEEE Trans. Circuits Syst. II Express Briefs 66–II(5):753–57. doi: 10.1109/TCSII.2019.2908243.

[90]. Wang, Jianfei, Li Jiang, Jing Ke, Xiaoyao Liang, and Naifeng Jing. 2019. “A Sharing-Aware L1.5D Cache for Data Reuse in GPGPUs.” Pp. 388–93 in Proceedings of the 24th Asia and South Pacific Design Automation Conference, ASPDAC 2019, Tokyo, Japan, January 21-24, 2019, edited by T. Shibuya. ACM.

[91]. Yuan, Geng, Xiaolong Ma, Caiwen Ding, Sheng Lin, Tianyun Zhang, Zeinab S. Jalali, Yilong Zhao, Li Jiang, Sucheta Soundarajan, and Yanzhi Wang. 2019. “An Ultra-Efficient Memristor-Based DNN Framework with Structured Weight Pruning and Quantization Using ADMM.” Pp. 1–6 in 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2019, Lausanne, Switzerland, July 29-31, 2019. IEEE.

2018

[92]. Ji, Houxiang, Linghao Song, Li Jiang*, Hai Helen Li, and Yiran Chen. 2018. “ReCom: An Efficient Resistive Accelerator for Compressed Deep Neural Networks.” Pp. 237–40 in 2018 Design, Automation & Test in Europe Conference & Exhibition, DATE 2018, Dresden, Germany, March 19-23, 2018, edited by J. Madsen and A. K. Coskun. IEEE.

[93]. Jiang, Li, Tianjian Li, Naifeng Jing, Nam Sung Kim, Minyi Guo, and Xiaoyao Liang. 2018. “CNFET-Based High Throughput SIMD Architecture.” IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(7):1331–44. doi: 10.1109/TCAD.2017.2695899.

[94]. Pang, Pu, Yixun Zhang, Tianjian Li, Sung Kyu Lim, Quan Chen, Xiaoyao Liang, and Li Jiang*. 2018. “In-Growth Test for Monolithic 3D Integrated SRAM.” Pp. 569–72 in 2018 Design, Automation & Test in Europe Conference & Exhibition, DATE 2018, Dresden, Germany, March 19-23, 2018, edited by J. Madsen and A. K. Coskun. IEEE.

[95]. Peng, Zhenghao, Xuyang Chen, Chengwen Xu, Naifeng Jing, Xiaoyao Liang, Cewu Lu, and Li Jiang*. 2018. “AXNet: Approximate Computing Using an End-to-End Trainable Neural Network.” P. 11:1-11:8 in Proceedings of the International Conference on Computer-Aided Design, ICCAD 2018, San Diego, CA, USA, November 05-08, 2018, edited by I. Bahar. ACM.

[96]. Song, Haiyue, Xiang Song, Tianjian Li, Hao Dong, Naifeng Jing, Xiaoyao Liang, and Li Jiang*. 2018. “A FPGA Friendly Approximate Computing Framework with Hybrid Neural Networks: (Abstract Only).” P. 286 in Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA 2018, Monterey, CA, USA, February 25-27, 2018, edited by J. H. Anderson and K. Bazargan. ACM.

[97]. Song, Haiyue, Chengwen Xu, Qiang Xu, Zhuoran Song, Naifeng Jing, Xiaoyao Liang, and Li Jiang*. 2018. “Invocation-Driven Neural Approximate Computing with a Multiclass-Classifier and Multiple Approximators.” P. 50 in Proceedings of the International Conference on Computer-Aided Design, ICCAD 2018, San Diego, CA, USA, November 05-08, 2018, edited by I. Bahar. ACM.

[98]. Wang, Chen, Yanan Sun, Shiyan Hu, Li Jiang, and Weikang Qian. 2018. “Variation-Aware Global Placement for Improving Timing-Yield of Carbon-Nanotube Field Effect Transistor Circuit.” ACM Trans. Design Autom. Electr. Syst. 23(4):44:1-44:27. doi: 10.1145/3175500.

[99]. Wang, Jianfei, Qin Wang, Li Jiang, Chao Li, Xiaoyao Liang, and Naifeng Jing. 2018. “IBOM: An Integrated and Balanced On-Chip Memory for High Performance GPGPUs.” IEEE Trans. Parallel Distributed Syst. 29(3):586–99. doi: 10.1109/TPDS.2017.2773516.

2017

[100]. Chen, Lerong, Jiawen Li, Yiran Chen, Qiuping Deng, Jiyuan Shen, Xiaoyao Liang, and Li Jiang*. 2017. “Accelerator-Friendly Neural-Network Training: Learning Variations and Defects in RRAM Crossbar.” Pp. 19–24 in Design, Automation & Test in Europe Conference & Exhibition, DATE 2017, Lausanne, Switzerland, March 27-31, 2017, edited by D. Atienza and G. D. Natale. IEEE.

[101]. Jing, Naifeng, Shunning Jiang, Shuang Chen, Jingjie Zhang, Li Jiang, Chao Li, and Xiaoyao Liang. 2017. “Bank Stealing for a Compact and Efficient Register File Architecture in GPGPU.” IEEE Trans. Very Large Scale Integr. Syst. 25(2):520–33. doi: 10.1109/TVLSI.2016.2584623.

[102]. Li, Tianjian, Xiangyu Bi, Naifeng Jing, Xiaoyao Liang, and Li Jiang*. 2017. “Sneak-Path Based Test and Diagnosis for 1R RRAM Crossbar Using Voltage Bias Technique.” P. 38:1-38:6 in Proceedings of the 54th Annual Design Automation Conference, DAC 2017, Austin, TX, USA, June 18-22, 2017. ACM.

[103]. Li, Tianjian, Yan Han, Xiaoyao Liang, Hsien-Hsin S. Lee, and Li Jiang*. 2017. “Fault Clustering Technique for 3D Memory BISR.” Pp. 560–65 in Design, Automation & Test in Europe Conference & Exhibition, DATE 2017, Lausanne, Switzerland, March 27-31, 2017, edited by D. Atienza and G. D. Natale. IEEE.

[104]. Wang, Jianfei, Fengfeng Fan, Li Jiang, Xiaoyao Liang, and Naifeng Jing. 2017. “Incorporating Selective Victim Cache into GPGPU for High-Performance Computing.” Concurr. Comput. Pract. Exp. 29(24). doi: 10.1002/CPE.4104.

[105]. Xu, Chengwen, Xiangyu Wu, Wenqi Yin, Qiang Xu, Naifeng Jing, Xiaoyao Liang, and Li Jiang*. 2017. “On Quality Trade-off Control for Approximate Computing Using Iterative Training.” P. 52:1-52:6 in Proceedings of the 54th Annual Design Automation Conference, DAC 2017, Austin, TX, USA, June 18-22, 2017. ACM.

2016

[106]. Fan, Fengfeng, Jianfei Wang, Li Jiang, Xiaoyao Liang, and Naifeng Jing. 2016. “Applying Victim Cache in High Performance GPGPU Computing.” Pp. 24–29 in 15th International Symposium on Parallel and Distributed Computing, ISPDC 2016, Fuzhou, China, July 8-10, 2016, edited by R. Chen, C. Rong, and D. Grigoras. IEEE Computer Society.

[107]. Jing, Naifeng, Li Jiang, Tao Zhang, Chao Li, Fengfeng Fan, and Xiaoyao Liang. 2016. “Energy-Efficient eDRAM-Based On-Chip Storage Architecture for GPGPUs.” IEEE Trans. Computers 65(1):122–35. doi: 10.1109/TC.2015.2417545.

[108]. Jing, Naifeng, Jianfei Wang, Fengfeng Fan, Wenkang Yu, Li Jiang, Chao Li, and Xiaoyao Liang. 2016. “Cache-Emulated Register File: An Integrated on-Chip Memory Architecture for High Performance GPGPUs.” P. 14:1-14:12 in 49th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2016, Taipei, Taiwan, October 15-19, 2016. IEEE Computer Society.

[109]. Li, Tianjian, Li Jiang*, Naifeng Jing, Nam Sung Kim, and Xiaoyao Liang. 2016. “CNFET-Based High Throughput Register File Architecture.” Pp. 662–69 in 34th IEEE International Conference on Computer Design, ICCD 2016, Scottsdale, AZ, USA, October 2-5, 2016. IEEE Computer Society.

[110]. Li, Tianjian, Li Jiang*, Xiaoyao Liang, Qiang Xu, and Krishnendu Chakrabarty. 2016. “Defect Tolerance for CNFET-Based SRAMs.” Pp. 1–9 in 2016 IEEE International Test Conference, ITC 2016, Fort Worth, TX, USA, November 15-17, 2016. IEEE.

[111]. Li, Tianjian, Feng Xie, Xiaoyao Liang, Qiang Xu, Krishnendu Chakrabarty, Naifeng Jing, and Li Jiang*. 2016. “A Novel Test Method for Metallic CNTs in CNFET-Based SRAMs.” IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(7):1192–1205. doi: 10.1109/TCAD.2015.2512909.

2015

[112]. Hua, Yiqing, Chao Li, Weichao Tang, Li Jiang, and Xiaoyao Liang. 2015. “Building Fuel Powered Supercomputing Data Center at Low Cost.” Pp. 241–50 in Proceedings of the 29th ACM on International Conference on Supercomputing, ICS’15, Newport Beach/Irvine, CA, USA, June 08 - 11, 2015, edited by L. N. Bhuyan, F. Chong, and V. Sarkar. ACM.

[113]. Jiang, Li, Xiangwei Huang, Hongfeng Xie, Qiang Xu, Chao Li, Xiaoyao Liang, and Huiyun Li. 2015. “A Novel TSV Probing Technique with Adhesive Test Interposer.” Pp. 597–604 in 33rd IEEE International Conference on Computer Design, ICCD 2015, New York City, NY, USA, October 18-21, 2015. IEEE Computer Society.

[114]. Jiang, Li, Pu Pang, Naifeng Jing, Sung Kyu Lim, Xiaoyao Liang, and Qiang Xu. 2015. “On Diagnosable and Tunable 3D Clock Network Design for Lifetime Reliability Enhancement.” Pp. 1–10 in 2015 IEEE International Test Conference, ITC 2015, Anaheim, CA, USA, October 6-8, 2015. IEEE.

[115]. Jiang, Li, and Qiang Xu. 2015a. “Fault-Tolerant 3D-NoC Architecture and Design: Recent Advances and Challenges.” P. 7:1-7:8 in Proceedings of the 9th International Symposium on Networks-on-Chip, NOCS 2015, Vancouver, BC, Canada, September 28-30, 2015, edited by A. Ivanov, D. Marculescu, P. P. Pande, J. Flich, and K. Pattabiraman. ACM.

[116]. Jiang, Li, and Qiang Xu. 2015b. “Yield and Reliability Enhancement for 3D ICs: Dissertation Summary: IEEE TTTC E.J. McCluskey Doctoral Thesis Award Competition Finalist.” Pp. 1–11 in 2015 IEEE International Test Conference, ITC 2015, Anaheim, CA, USA, October 6-8, 2015. IEEE.

[117]. Jing, Naifeng, Shuang Chen, Shunning Jiang, Li Jiang, Chao Li, and Xiaoyao Liang. 2015. “Bank Stealing for Conflict Mitigation in GPGPU Register File.” Pp. 55–60 in IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2015, Rome, Italy, July 22-24, 2015. IEEE.

[118]. Li, Tianjian, Hao Chen, Weikang Qian, Xiaoyao Liang, and Li Jiang*. 2015. “On Microarchitectural Modeling for CNFET-Based Circuits.” Pp. 356–61 in 28th IEEE International System-on-Chip Conference, SOCC 2015, Beijing, China, September 8-11, 2015. IEEE.

[119]. Sun, Zelong, Li Jiang, Qiang Xu, Zhaobo Zhang, Zhiyuan Wang, and Xinli Gu. 2015. “On Test Syndrome Merging for Reasoning-Based Board-Level Functional Fault Diagnosis.” Pp. 737–42 in The 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015, Chiba, Japan, January 19-22, 2015. IEEE.

[120]. Wang, Chen, Li Jiang, Shiyan Hu, Tianjian Li, Xiaoyao Liang, Naifeng Jing, and Weikang Qian. 2015. “Timing-Driven Placement for Carbon Nanotube Circuits.” Pp. 362–67 in 28th IEEE International System-on-Chip Conference, SOCC 2015, Beijing, China, September 8-11, 2015. IEEE.

[121]. Xie, Feng, Xiaoyao Liang, Qiang Xu, Krishnendu Chakrabarty, Naifeng Jing, and Li Jiang*. 2015. “Jump Test for Metallic CNTs in CNFET-Based SRAM.” P. 16:1-16:6 in Proceedings of the 52nd Annual Design Automation Conference, San Francisco, CA, USA, June 7-11, 2015. ACM.

[122]. Zhang, Xiaolong, Huiyun Li, Li Jiang, and Qiang Xu. 2015. “A Low-Cost TSV Test and Diagnosis Scheme Based on Binary Search Method.” IEEE Trans. Very Large Scale Integr. Syst. 23(11):2639–47. doi: 10.1109/TVLSI.2014.2362560.

2013

[123]. Jiang, Li, Qiang Xu, and Bill Eklow. 2013. “On Effective Through-Silicon Via Repair for 3-D-Stacked ICs.” IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(4):559–71. doi: 10.1109/TCAD.2012.2228742.

[124]. Jiang, Li, Fangming Ye, Qiang Xu, Krishnendu Chakrabarty, and Bill Eklow. 2013. “On Effective and Efficient In-Field TSV Repair for Stacked 3D ICs.” P. 74:1-74:6 in The 50th Annual Design Automation Conference 2013, DAC ’13, Austin, TX, USA, May 29 - June 07, 2013. ACM.

[125]. Sun, Zelong, Li Jiang, Qiang Xu, Zhaobo Zhang, Zhiyuan Wang, and Xinli Gu. 2013. “AgentDiag: An Agent-Assisted Diagnostic Framework for Board-Level Functional Failures.” Pp. 1–8 in 2013 IEEE International Test Conference, ITC 2013, Anaheim, CA, USA, September 6-13, 2013. IEEE Computer Society.

2012

[126]. Jiang, Li, Qiang Xu, Krishnendu Chakrabarty, and T. M. Mak. 2012. “Integrated Test-Architecture Optimization and Thermal-Aware Test Scheduling for 3-D SoCs Under Pre-Bond Test-Pin-Count Constraint.” IEEE Trans. Very Large Scale Integr. Syst. 20(9):1621–33. doi: 10.1109/TVLSI.2011.2160410.

[127]. Jiang, Li, Qiang Xu, and Bill Eklow. 2012. “On Effective TSV Repair for 3D-Stacked ICs.” Pp. 793–98 in 2012 Design, Automation & Test in Europe Conference & Exhibition, DATE 2012, Dresden, Germany, March 12-16, 2012, edited by W. Rosenstiel and L. Thiele. IEEE.

[128]. Xu, Qiang, Li Jiang, Huiyun Li, and Bill Eklow. 2012. “Yield Enhancement for 3D-Stacked ICs: Recent Advances and Challenges.” Pp. 731–37 in Proceedings of the 17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012, Sydney, Australia, January 30 - February 2, 2012. IEEE.

2010

[129]. Jiang, Li, Yuxi Liu, Lian Duan, Yuan Xie, and Qiang Xu. 2010. “Modeling TSV Open Defects in 3D-Stacked DRAM.” Pp. 174–82 in 2011 IEEE International Test Conference, ITC 2010, Austin, TX, USA, November 2-4, 2010, edited by R. Press and E. H. Volkerink. IEEE Computer Society.

[130]. Jiang, Li, Rong Ye, and Qiang Xu. 2010. “Yield Enhancement for 3D-Stacked Memory by Redundancy Sharing across Dies.” Pp. 230–34 in 2010 International Conference on Computer-Aided Design, ICCAD 2010, San Jose, CA, USA, November 7-11, 2010, edited by L. Scheffer, J. R. Phillips, and A. J. Hu. IEEE.

2009

[131]. Jiang, Li, Lin Huang, and Qiang Xu. 2009. “Test Architecture Design and Optimization for Three-Dimensional SoCs.” Pp. 220–25 in Design, Automation and Test in Europe, DATE 2009, Nice, France, April 20-24, 2009, edited by L. Benini, G. D. Micheli, B. M. Al-Hashimi, and W. Müller. IEEE.

[132]. Jiang, Li, Qiang Xu, Krishnendu Chakrabarty, and T. M. Mak. 2009. “Layout-Driven Test-Architecture Design and Optimization for 3D SoCs under Pre-Bond Test-Pin-Count Constraint.” Pp. 191–96 in 2009 International Conference on Computer-Aided Design, ICCAD 2009, San Jose, CA, USA, November 2-5, 2009, edited by J. S. Roychowdhury. ACM.